Several techniques have been used to address the leakage problem; for instance some techniques propose using only high performance LVT circuits in the critical path and slower circuits, such as HVT device, with less leakage elsewhere on the chip. Circuit libraries are available in several variations of VTs, which can be mixed and matched throughout the chip. Very complex chip methodologies are used to determine where a HVT circuit should be used in place of a Low VT (LVT) circuit to increase performance.
In one prior approach, a method and system for determining optimal delay allocation to data path blocks is based on area-delay and power-delay curves. In particular this method, system and computer program product automatically determine optimal design parameters of a subsystem to meet design constraints. The subsystem includes a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters.
Another solution is, in a standby state, the use of substrate bias to reduce leakage. In functional mode there is no performance degradation. Dual Threshold voltage is a well-known approach to reduce leakage by partitioning the circuit based on the speed/performance requirements.
In connection with such a Dual Threshold Voltages strategy, another approach for power management includes first synthesis step performed using high-Vt transistor, while low-Vt are used to close the timing constraints.
We will make hereinafter more specific reference to the SYNOPSYS tools that are known for reducing power at an average of 10 to 20 percent during gate-level optimization.
Based on user's timing, power and area constraints, these tools measures trade-offs between positive timing slacks, area and power and then deliver the lowest power consuming design that meets timing constraints, while maintaining the area limit when specified by the user. Power Compiler performs automatic clock gating at the Register Transfer Level (RTL) and it also supports multi-threshold libraries for automatic leakage optimization. Incremental synthesis allows starting with all high threshold voltage cells and substituting a small percentage of them with low threshold voltage ones for critical paths. After place and route, the substitution of high Vt cells with low Vt ones after paths are analyzed with precise timing information is implemented.
A further tool does multi-Vt leakage power optimization. Moreover, these tools are capable of minimizing the leakage during the synthesis step through the clock gating approach and, following P&R, the multi-Vt optimization is done.
Another approach proposed by tool vendors is based on the fact that the leakage current of a gate mainly depends on the state of the input signals. If a vector can be found that minimizes the leakage current, then this vector can be applied when the circuit is idle. However, it's quite a hard job to find such an optimal vector as the logic depth increases.
A SIGNOFF static timing analysis (STA) is performed after the place and route of the block. The main issues with this approach are related to critical paths at high frequency, in the range of 1 GHz, where the timing closure is a must despite the power consumption, leakage and area. On the other end, on paths at lower frequencies where the positive slacks are quite large, it is possible to reduce the leakage by slowing down some data delays thus losing timing margin but still maintaining require specifications.
All the known methodologies above described, whilst enabling a decrease of power consumption, nevertheless have a recognized drawback not yet overcome, that the obtained decrease of leakage often affects the ability to achieve or respect the timing requirements.
In view of the above-outlined drawback of the state of the art, there is the need of providing a method and system to implement application specific integrated circuit (ASIC) designs in order to reduce leakage without affecting the timing requirements.